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previously selected Ultra DMA mode and revert to the default non-Ultra DMA modes after executing a
power-on or hardware reset.
Both the host and device perform a CRC function during an Ultra DMA burst. At the end of an Ultra DMA
burst the host sends its CRC data to the device. The device compares its CRC data to the data sent from the
host. If the two values do not match, the device reports an error in the error register. If an error occurs
during one or more Ultra DMA bursts for any one command, the device shall report the first error that
occurred. If the device detects that a CRC error has occurred before data transfer for the command is
complete, the device may complete the transfer and report the error or abort the command and report the
error.
NOTE ? If a data transfer is terminated before completion, the assertion of INTRQ should be passed through
to the host software driver regardless of whether all data requested by the command has been transferred.
6.3.1.1 UDMA Address and Card Select Signals
The Card Select signals -CS0 and -CS1) shall remain negated during Ultra DMA data bursts.
The Address bus (A[2:0]) shall not transition unnecessarily during the UDMA command and shall remain
fixed during an Ultra DMA data burst. In True IDE mode, the address lines (A[2:0]) shall be held to all zeros.
This will reduce unnecessary noise during the UDMA command.
6.3.1.2 Task File registers shall not be written during an Ultra DMA command
The task file registers shall not be written after an Ultra DMA command is issued by the host and before the
command completes. Writing to the device control register is permitted between bursts, but is expected to
occur only to reset the drive after an unrecoverable protocol error.
6.3.1.3 Ultra DMA transfers shall be 16 bits wide
All transfers during an Ultra DMA data burst are 16 bit wide transfers. The Set Features command that
controls the bus width for PIO transfers does not affect the width of Ultra DMA transfers.
6.3.2 Ultra DMA Phases of Operation
An Ultra DMA data transfer is accomplished through a series of Ultra DMA data-in or data-out bursts. Each
Ultra DMA burst has three mandatory phases of operation: the initiation phase, the data transfer phase,
and the Ultra DMA burst termination phase. In addition, an Ultra DMA burst may be paused during the data
transfer phase (see: 6.3.2.4 , for the detailed protocol descriptions for each of these phases. Table 22: Ultra
DMA Data Burst Timing Requirements and Table 23: Ultra DMA Data Burst Timing Descriptions define the
specific timing requirements). In the following rules -DMARDY is used in cases that could apply to either -
DDMARDY or -HDMARDY, and STROBE is used in cases that could apply to either DSTROBE or HSTROBE. The
following are general Ultra DMA rules.
1.
2.
An Ultra DMA burst is defined as the period from an assertion of -DMACK by the host to the
subsequent negation of -DMACK.
When operating in Ultra DMA modes 2, 1, or 0 a recipient shall be prepared to receive up to two
data words whenever an Ultra DMA burst is paused. When operating in Ultra DMA modes 6, 5, 4, or
3 a recipient shall be prepared to receive up to three data words whenever an Ultra DMA burst is
paused.
6.3.2.1 Ultra DMA Burst Initiation Phase Rules
1.
2.
3.
4.
5.
6.
7.
An Ultra DMA burst initiation phase begins with the assertion of DMARQ by a device and ends when
the sender generates a STROBE edge to transfer the first data word.
An Ultra DMA burst shall always be requested by a device asserting DMARQ.
When ready to initiate the requested Ultra DMA burst, the host shall respond by asserting -DMACK.
A host shall never assert -DMACK without first detecting that DMARQ is asserted.
For Ultra DMA data-in bursts: a device may begin driving D[15:00] after detecting that -DMACK is
asserted, STOP negated, and -HDMARDY is asserted.
After asserting DMARQ or asserting -DDMARDY for an Ultra DMA data-out burst, a device shall not
negate either signal until the first STROBE edge is generated.
After negating STOP or asserting -HDMARDY for an Ultra DMA data-in burst, a host shall not change
the state of either signal until the first STROBE edge is generated.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.00
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
P-120_data_sheet_PA-QxBO_Rev100.doc
Page 15 of 76
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